On-chip Process Variation Detection and Compensation for Parametric Yield Enhancement in sub-100nm CMOS technology

The need for efficient compensation schemes to counter the impact of process variations on the parametric yield of designs has increased in the nm design era. In this paper, a process variation compensation technique that uses both delay and slew metrics has been proposed to determine the optimal NMOS and PMOS body-bias voltages to improve parametric yield of the designs. The need to consider both these metrics has been illustrated and an analytical framework has been presented to establish the relationship of the appropriate bias voltage to be applied based on the sensor outputs. Preliminary simulation results of the compensation scheme circuitry have been presented.